Composite video is a communications signal which contains color video information (which includes the chrominance signal conveyed by means of a subcarrier) as well as timing information for the accurate reproduction of the active video (e.g. reproduction of the picture information including its correct colors). This signal is essentially a video stream that combines, as a one signal, all of the elements required for displaying an image. The timing information is conveyed through the transmission of synchronization signals. A synchronization signal is commonly referred to as sync. In conjunction with a receiver which displays pixel information according to the video picture transmitted, an electric beam scans the receiver's display according to the horizontal sync signal followed by a horizontal blanking interval during which time the beam is shut off so that it can spot retrace horizontally across the display without being observed. Once the display has been scanned from top to bottom, the vertical sync signal determines when the beam is returned to the top of the display during the vertical blanking interval during which time the beam is shut off so that it can spot retrace vertically across the display without being observed. A composite video signal generally includes active video, horizontal sync, horizontal blanking, vertical sync, vertical blanking, and color burst. The color burst is that portion of the video waveform that sits between the breezeway (the portion of the video waveform between the rising edge of the horizontal sync and the start of the color burst) and the start of the active video. The color burst allows the color decoder to decode the color information contained in a line of active video. In a receiver or video decoder, the color phase locked-loop maintains lock of the local color oscillator with the color burst of the composite video input signal.
Conventional horizontal phase-locked loops for video decoders serve the purpose of locking the sampling clock, for clocking digital pixel information into the phase-locked loop, to the falling edge of the incoming horizontal sync of composite video information. This lock is required to generate a stable picture in the horizontal direction and position signals which identify the sync tip, back porch, and the color burst of the composite video. The analog video information enters an analog-to-digital converter which outputs digital pixel information. A pixel counter counts video information corresponding to pixels in what can be considered a horizontal scan line across a display monitor screen such as a cathode ray tube. The pixel counter starts with a count of zero and counts to a terminal count and then falls back to zero. The phase-locked loop employs two modes of lock; a coarse lock and a fine lock. In the coarse lock mode the incoming horizontal sync pulse which is usually present during the blanking interval of each line associated with the video signal (for the purpose of being able to synchronize the scanning of the monitor with the scanning of the original image), is detected by an analog circuit. Based on the decode of the pixel counter, a coarse gate filter window (meaning a relatively wide time window in comparison with the narrow time window associated with the fine window discussed below) is enabled around the time the horizontal sync pulse is expected. If the sync does not occur within the gate window for a time corresponding to several consecutive video lines, then either the pixel counter is reset or a correction is made to the clock frequency of the video decoder system in order to move the window to the sync pulse. When the sync pulse falls within the fine lock window, then the fine lock mode is enabled. A fine gate filter window is employed by the fine lock mode which enables a phase detector which calculates a phase error based upon the position of the edge of the sync pulse within a narrow window known as the fine lock window. This phase error is then filtered by a loop filter whose output is fed to a discrete time oscillator which adjusts the clock frequency to move the sync pulse so that its edge is centered in the fine window, thereby minimizing the phase error. Prior art horizontal phase-locked loop schemes are generally implemented according to analog hardware, digital hardware or a combination of analog and digital hardware. A major drawback of this type of implementation lies in the inconvenience of changing parameters to adapt to a particular video scheme, e.g. NTSC, PAL, NPAL, MPAL, etc.
The color phase lock loop is normally controlled by generating the phase error between the color burst input and the locally generated color frequency. The phase error is computed during the color burst interval by accumulating the product of the color burst input pixels and the cosine of the local color oscillator cos w.sub.sc t. The phase error is then filtered and added to a nominal color DTO increment value and then written to the color DTO. This occurs once per scan line. The phase error may also be accumulated in a register such that any frequency offset may be detected and added to the color DTO increment. This technique works fine if the pixel clock frequency is stable. However, should the pixel clock frequency vary (as it can with VCR (video cassette recorder) inputs), problems can arise in efforts to accurately reproduce color content on a display. A microprocessor based system is needed in order provide a highly adaptable and improved horizontal phase-locked loop as well as an improved color phase-locked loop.